1. Field of the Invention
The present invention generally relates to the field of computer systems. More particularly, the present invention relates to methods and arrangements for managing power and energy in processors of computer systems.
2. Description of the Related Art
The competitive nature of industries has increased reliance on computer systems to perform daily operations, increasing the demand for fast and reliable computer systems with reasonable size and space requirements. The speed, or processing power, of computer systems in the same or smaller packages has led contemporary computer designs toward smaller chips that operate at higher frequencies, inherently increasing power densities within the IC chips. However, the higher frequencies and increased power densities also decrease reliability.
Traditionally, power expenditures by processors are controlled by reducing the voltages and frequencies of processors. For example, in laptops, power may be considered a premium while the laptop is operating strictly off of battery power. Thus, processors for many laptops include various power saving modes of operation that include shutting down parts of the processor and reducing the voltage and frequency for the core(s) while the processing capacity of the processor is not fully utilized.
Modern processors operate at very high frequencies and are projected to reach 20–40 gigahertz (GHz) in the next five to ten years. At such frequencies, small processor cores generate very high power densities even when their voltages and frequencies are reduced. These high power densities subject modern processors to very high failure rates.
The decreased reliability has led many manufacturers toward autonomic computing designs. Autonomic computing refers to computer systems that configure themselves to changing conditions and are self healing in the event of failure. For instance, if one server in a rack of servers fails, the workload for the failed server may be shifted to another server in the rack, allowing operations to continue, albeit, possibly with lower processing capability and, potentially, at a slower processing rate. Nonetheless, fewer failures are catastrophic and less human intervention is required for routine operation.
Autonomic designs may also be incorporated on the IC chip level by incorporating redundant systems of subcomponents for subcomponents that tend to fail such as ports of arrays like register files. Adding redundant systems in a processor core, however, represents a solution for the effect, i.e., high failure rates, rather than a solution for the high power densities. Further, redundant systems both increase the silicon area utilized by the core and slow down the core. Depending upon the number of metallization layers available within a processor, adding redundant components can involve a linear expansion of silicon area, which significantly impacts the costs of manufacturing the processor and the speed with which instructions can be processed by the processor.
Therefore, there is a need for methods and arrangements for dynamically adjusting power densities of processor cores, balancing power and energy expenditures with performance demands, to attenuate or minimize failure rates associated with processor cores.